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Phase Lock Loop (PLL)

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ReceiversReceivers
Title Phase Lock Loop (PLL)
Edited by GMV
Level Advanced
Year of Publication 2011
Logo GMV.png

Phase Lock Loops are part of the receiver's signal tracking loops, and aim at tracking the phase of the incoming GNSS signal. The PLL provides a correction of the phase in a continuous loop, generating a phase error signal.

Principle

The Phase Lock Loop (PLL) tracks and estimates the current misalignment between the Prompt correlator and the incoming signal phase, within the tracking loops. For that purpose, the PLL uses integrations, filters and Numerical Control Oscillators (NCO) – described here – as any other typical loop. In this case, the specificity relies on the discriminator used to assess the current phase error estimated at the receiver.

Figure 1: Representation of the Prompt Correlator output.

As elaborated here, the output of the correlation and accumulation blocks can be written in its In-phase (I) and Quadrature (Q) components as:



where:

  • is the auto-correlation of the X PRN code.
  • stands for the Prompt replica, i.e. the replica generated at the receiver which is aligned with the incoming signal.
  • is the error of the code delay estimated at the receiver.
  • is the error of the carrier phase estimated at the receiver.


Figure 1 represents the output of the In-phase and Quadrature components of the prompt correlator. When tracking the signal correctly, the prompt vector should be, ideally, in the In-phase axis (with no Quadrature component). Therefore, the phase error can be retrieved from the phase of the correlator using and , and the PLL will feedback a new carrier correction in order to minimize this error.

Discriminators

Two types of PLL discriminators are often mentioned[1]:


  • Sensitive to bit transitions, hence phase shifts:

The most common discriminator sensitive to bit transitions is given by:



which is optimal, but presents a high computational burden. In order to use such discriminator, the receiver must ensure that the inputs do not include bit transitions, e.g. doing data wipe-off during the integration.


  • Insensitive to bit transitions, also called Costas loop:

The classic Costas loop discriminator (the near optimal) can be written as:



and another example of Costas loops is given by:



The choice of the discriminator is a trade-off between performance of the PLL and required hardware resources, as well as complexity.

Performance

The main sources of errors in the PLL are phase jitter and dynamic stress error[1], which are mainly produced by thermal noise. The PLL thermal noise jitter for an arctangent PLL can be written (in meters) as:



where:

  • is wavelength of the carrier signal [m].
  • is the loop bandwidth [Hz].
  • is the carrier to noise ratio [Hz].
  • is the integration time [s].


The performance of the PLL depends mainly on the loop bandwidth and the integration times used to accumulate the correlator outputs. The impact of these parameters is shown in Figure 2, and they are visible mainly for low carrier to noise ratio.

Figure 2: Impact of loop bandwidth (left) and integration time (right) on the PLL thermal noise jitter performance.

These results also illustrate the fact that longer integration times (and lower bandwidths) lead to noise reduction, hence higher performances, as discussed here.

Related articles

References

  1. ^ a b Kaplan E.D., Hegarty C.J., "Understanding GPS: Principles and Applications", second edition.